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DVFS based power management for LDPC decoders with early termination

Type of publication Peer-reviewed
Publikationsform Proceedings (peer-reviewed)
Author Ghanaatian Reza, Burg Andreas,
Project Design of Energy Efficient and Wireless Communication Systems under Unreliable Silicon
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Proceedings (peer-reviewed)

Title of proceedings 2017 IEEE International Workshop on Signal Processing Systems (SiPS)
Place Lorient
DOI 10.1109/sips.2017.8109981


Low-density parity check (LDPC) codes are a mature coding scheme in telecommunications and the low power implementation of corresponding decoders is an issue of significant importance for receivers with stringent power budgets. This paper presents a power reduction technique for LDPC decoders that further extends their energy-proportional behavior, obtained with early-termination (ET), by predicting the required number of iterations and by applying dynamic voltage and frequency scaling (DVFS). The number of expected iterations and the associated voltage/frequency settings are predicted with a novel algorithm that is based on the offline statistical analysis of the number of decoding iterations. This algorithm systematically trades the error-correcting performance up to a predefined approximation level for the achieved amount of power reduction beyond ET. Simulation and postlayout implementation results in a 28 nm FD-SOI technology prove that the proposed algorithm, when integrated with an LDPC decoder, can significantly reduce the power consumption with negligible overhead.