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Mapping Matters: Application Process Mapping on 3-D Processor Topologies

Type of publication Peer-reviewed
Publikationsform Proceedings (peer-reviewed)
Author Müller Korndörfer Jonas Henrique, Bielert Mario, Pilla Laércio L., Florina M. Ciorba,
Project Multilevel Scheduling in Large Scale High Performance Computers
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Proceedings (peer-reviewed)

Title of proceedings The International Conference on High Performance Computing & Simulation (HPCS2020)
Place Barcelona, Spain

Open Access

URL https://arxiv.org/abs/2005.10413
Type of Open Access Repository (Green Open Access)

Abstract

Applications’ performance is influenced by the mapping of processes to computing nodes, the frequency and volume of exchanges among processing elements, the network capacity, and the routing protocol. A poor mapping of application processes degrades performance and wastes system resources. As process mapping is frequently ignored as an explicit optimization step (since the system typically offers a default mapping), users may lack awareness of their applications’ communication behavior, making the opportunities for improving performance through careful mapping often unclear. This work studies the impact of application process mapping on several processor topologies. We propose and apply a generic workflow that renders mapping as an explicit optimization step to a set of four applications, twelve mapping algorithms, and three direct network topologies. We assess the mappings’ quality in terms of volume, frequency, and distance of exchanges using metrics such as dilation (measured in hop·Byte). With a parallel trace-based simulator, we predict the applications’ execution on the three topologies using the twelve mappings. To ensure the correctness of the simulations, we compare the pre- and post-simulation results. This work emphasizes the importance of process mapping as an explicit optimization step and, thereby, offers a solution for parallel applications to exploit the full potential of the allocated resources on a given system.
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