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Proof of Concept for Large Ultra-High Density Embedded Memories

English title Proof of Concept for Large Ultra-High Density Embedded Memories
Applicant Giterman Robert
Number 198692
Funding scheme Bridge - Proof of Concept
Research institution
Institution of higher education EPF Lausanne - EPFL
Main discipline Electrical Engineering
Start/End 01.05.2021 - 31.10.2022
Approved amount 123'664.00
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All Disciplines (2)

Electrical Engineering
Microelectronics. Optoelectronics

Keywords (3)

Embedded Memory; Circuits and Systems; SRAM

Lay Summary (German)

Eingebettete Speicher in modernen integrierten Schaltungen erreichen oft die Grösse von vielen hundert Megaits die dann bis zu 75% der Chipfläche beanspruchen. Speicher besteht heutzutage aus SRAM, das in Form einer Vielzahl gleicher oder ähnlicher IP Makros hundertfach in Schaltungen integriert wird. Jede Verbesserung dieser grundlegenden IP Marko hat daher einen überragenden Einfluss auf den Preis fast aller integrierten Schaltungen.
Lay summary

Während heutige 6T SRAMs zwischen 6 und 8 Transistoren pro Bit benötigen, speichert Gain-Cell Embedded DRAM (GC-eDRAM) Daten als Ladungen und kommt daher mit nur 2-3 Transistoren pro Bit aus. GC-eDRAM Speicher sind daher um bis zu 50% kleiner als SRAM oder bieten die doppelte Speichermenge in der gleichen Fläche (bei gleichen Kosten). Ähnlich wie bei SRAM existieren verschiedene Formen von GC-eDRAM (2T, 3T, 4T, …) die sich durch unterschiedliche Tradeoffs zwischen Fläche, Retention Time, Geschwindigkeit oder Power auszeichnen.

Unsere Arbeit basiert auf einem Jahrzehnt führender Forschung im Bereich eingebetteter Speicher. Insbesondere unsere Arbeit an GC-eDRAMs ist in mehr als 20 Peer-Reviewed Konferenzen, Zeitschriften und Büchern erschienen und ist durch 2 bereits akzeptierte und 6 eingereichte Patente geschützt.

Das Ziel dieses Projektes und ein notwendiger Schritt zur Vermarktung unserer Technologie ist die industrielle Qualifizierung und Zertifizierung eines grossen GC-eDRAM Speicher Bausteins als „Proof of Concept“. Das Resultat des Projektes ist der Schlüssel zur Akzeptanz unserer Forschung durch potenzielle Kunden die unsere Technologie in der Massenproduktion einsetzen wollen. Der Prototyp aus diesem Projekt ist damit unsere Eintrittskarte in den IP Markt.

Direct link to Lay Summary Last update: 27.04.2021

Responsible applicant and co-applicants



CMOS systems-on-chips (SoCs) are the basic building blocks of modern technologies ranging from every-day products such as cell-phones, laptops, cars, or remote controls to ICT infrastructure including data centers, communication networks, or smart grids. However, a closer look at many of these products reveals that with the ultra-large scale integration of modern processes technologies, the functional blocks could be realized in much smaller die area and therefore lower cost, as in fact, the majority of the chip area is only utilized for embedded memory blocks. These on-chip embedded memories are used to store data close to the processing units in order to reduce the energy and latency overheads as well as the cost associated with on-chip standalone memory ICs. Static random access memory (SRAM) is the predominant technology for embedded memories; however, SRAMs require a large amount of area since storing a single data bit requires at least six (6) transistors. In fact, today, over 50% of the silicon real estate of almost any digital SoC is only covered by memory. Furthermore SRAM suffers from high static power consumption and the inherent sensitivity of SRAM to reliability issues in the manufacturing process often prevents the use of advanced low-power design-techniques.Our Gain-cell embedded DRAM (GC-eDRAM) technology requires only 2-4 transistors for each bit (as opposed to 6{8 for SRAM) and data is kept as electrical charge on parasitic transistor capacitances. As opposed to other (emerging) high-density memory technologies, GC-eDRAM is compatible with any standard CMOS process and requires no costly additional masks or process steps. The lower transistor count per bit-cell and the specic bit-cell circuit provide up-to 50% area reduction and up-to 3x lower power consumption than conventional SRAM technology and enable up to 2x higher memory access bandwidth through independent read- and write ports. More on-chip memory can even eliminate external memory access, delivering orders of magnitude power reduction. Replacing conventional SRAM IPs with the developed GC-eDRAM technology in commercial products is therefore expected to bring signicant benets in area, power, and bandwidth, thanks to the higher density and lower power consumption of our technology. So far, our research on GC-eDRAM has been documented by more than 20 peer-reviewed scientic publications in books, journals, conference proceedings and key inventions are protected by six (6) submitted patents. As part of this research, more than ten (10) silicon prototypes have been developed in various process technologies ranging from 180 nm{28nm processes to prove the viability and the potential of the technology, demonstrating signicant density and power benets over conventional embedded memory (i.e., SRAM) options. The objective of this project and a necessary step toward the commercialization of the technology is the industrial qualication of a large proof-of-concept memory macro based on GC-eDRAM technology. In order to bring our technology to the market, we will collaborate with a few selected industry partners with high-volume products, which are burdened by large amounts of embedded memory. Based on this analysis, a memory macro will be implemented using standard IC design and layout tools and extensive simulations will be used to verify its functionality and performance. The macro will then be fabricated as a stand-alone test chip to perform a detailed silicon validation as requested by potential customers prior to integration in one of their products.The outcome of this project will be instrumental to extend our academic results to the expectations of potential customers that will use our macros in mass production. As such, this prototype will serve as entry-ticket to the memory IP market.