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Understanding processing-induced defects to improve semiconductor device manufacturing technology

Applicant Prokscha Thomas
Number 192218
Funding scheme Project funding
Research institution Paul Scherrer Institut
Institution of higher education Paul Scherrer Institute - PSI
Main discipline Condensed Matter Physics
Start/End 01.10.2020 - 30.09.2024
Approved amount 625'320.00
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Keywords (7)

SiC power devices; semiconductor manufacturing; semiconductor-oxide interfaces; Defects in semiconductors; semiconductor processing; low-energy muon spin rotation; deep-level transient spectroscopy

Lay Summary (German)

Lead
Mit zunehmendem weltweiten Energieverbrauch bekommt der Einsatz von energieeffizienten elektronischen Bauelementen immer grössere Bedeutung. Es wird geschätzt, dass etwa 60% des Energieverbrauchs im Jahr 2040 auf elektrischer Energie basiert. Derzeit gehen weltweit etwa 10% der elektrischen Energie aufgrund von Wärmeverlusten während der Übertragung vom Erzeuger zum Verbraucher verloren. Daher ist die Entwicklung von effizienteren elektronischen Bauelementen, wie z.B. Hochleistungstransistoren, von grundlegender Bedeutung zur Reduktion des weltweiten Energieverbrauches. Der Halbleiter Silizium Carbid (SiC) ist dabei ein vielversprechender Kandidat, um zukünftige Hochleistungstransistoren mit niedrigen Wärmeverlusten zu entwickeln.
Lay summary
Hochleistungstransistoren aus SiC haben eine dünne Oxidschicht aus Siliziumdioxid auf einer schwach dotierten SiC Schicht. Mit Anlegen eines elektrischen Feldes an der Oxidschicht kann der elektrische Widerstand der SiC Schicht so beeinflusst werden, dass sehr hohe Ströme ein- und ausgeschaltet werden können. Ein Problem besteht derzeit darin, dass die Grenzschicht zwischen Oxid und SiC Kristalldefekte enthält, die zu Wärmeverlusten im leitenden Zustand führen.

Das Ziel unseres Projektes ist die Verbesserung der Oxid/SiC Grenzschicht durch Kombination einer neuen,
tiefenaufgelösten Charakerisierungsmethode zum Nachweis von Kristalldefekten mit Standardherstellungs- und -charakterisierungsverfahren. Durch Optimierung des Herstellungsprozesses soll die Defektkonzentration in der Nähe der Grenzschicht minimiert werden. Gleichzeitig soll ein besseres Verständnis der Defektentstehung an Halbleitergrenzschichten erreicht werden, um die bisher wenig verstandene Beziehung zwischen prozess-induzierten Defekten und Limitierungen der Zuverlässigkeit und Leistung von elektronischen Bauelementen zu untersuchen.
Direct link to Lay Summary Last update: 26.10.2020

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Abstract

With the continuous increase of the worldwide power consumption, energy efficiency is a primary concern of our modern society. By 2040, 60% of the consumed energy will be presented by electrical energy and new strategies to efficiently store, distribute and convert electricity are becoming increasingly important. Considering that currently around 10% of the electrical energy is lost as heat during various transformation processes on the way from the generation to the end consumer, the development of more efficient power electronic devices is essential for a reduction of the world-wide energy consumption. Silicon Carbide (SiC) has received increasing attention as a wide-bandgap semiconductor suitable for advanced high-voltage power devices with low losses. Although there are many similarities to established Si process technologies, SiC-based power electronics require a number of modified fabrication steps and fundamental understanding of the material properties and the reliability of state-of-the-art SiC devices is still poor. Especially the growth of high-quality SiC epitaxial layers as well as doping control and oxide growth during subsequent device fabrication remain major challenges on the way towards a new generation of SiC-based power electronics. Interestingly, as for most electronic devices, also SiC ones often rely on effects dominated by surfaces and interfaces rather than pure bulk properties. Here, there is a clear advantage for surface-sensitive techniques to be utilized for further improvement in processing.There exist a variety of characterization methods - either on material or on device level - which are used to investigate processing-induced defects both in the SiC epixtaxial layer and at the oxide/SiC interface. However, most of them lack the ability to resolve shallow defects close to the SiC surface. A powerful technique for a depth-resolved defect analysis is low-energy muon spin rotation (LE-µSR), available at the Swiss Muon Source SµS at the Paul-Scherrer Institute. While main applications of LE-µSR are related to the investigation of spatial and temporal properties of local magnetic fields in thin-film and multi-layered structures, its potential for the characterization of semiconductor defects was shown only recently. The ability to electrically probe and spatially resolve shallow defects in the semiconductor is a unique feature of LE-µSR and, in combination with deep-level transient spectroscopy (DLTS) for the characterization of electrical defects, a powerful tool to obtain a comprehensive picture of the defect generation during the fabrication process. Aim of this proposal is to combine LE-µSR defect studies of SiC and its near-interface region with the electrical analysis of SiC devices and dedicated test structures. Studying the mechanisms of defect generation both on an atomistic and on an applied level will allow to address the poorly understood relation between process-induced defects and observed limitations in device reliability and performance. Ultimately, this will enable solving practical processing challenges and the root-cause for reliability issues in power semiconductor devices.
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