Project

Back to overview

Magic ISEs: Enlarging the Scope of Automatic Instruction Set Extension

Applicant Pozzi Laura
Number 156397
Funding scheme Project funding (Div. I-III)
Research institution Istituto di sistemi informatici (SYS) Facoltà di scienze informatiche
Institution of higher education Università della Svizzera italiana - USI
Main discipline Information Technology
Start/End 01.11.2014 - 31.08.2019
Approved amount 583'927.00
Show all

Keywords (6)

Reconfigurable Processors; Automatic Instruction Set Extensions; Customizable Processors; ASIPs; Accelerators; Heterogeneous Computing

Lay Summary (Italian)

Lead
I processori customizzabili sono processori che possono essere ottimizzati a seconda della applicazione che devono eseguire. Customizzando un processore si puo' ottenere una performance molto migliore, e un consumo di potenza molto piu' basso, rispetto a quello che si otterrebbe usando un processore general-purpose-e quindi non customizzato.Nello specifico, un modo efficiente di customizzare un processore e' quello di affiancargli dell’hardware aggiuntivo, nel quale si possa eseguire una parte importante della applicazione, in maniera dedicata. L’identificazione di queste parti critiche dell’applicazione, cosi' come la loro implementazione in hardware, richiedono pero' tipicamente l’intervento manuale del progettista.In questo progetto, si identificano algoritmi che siano in grado di selezionare e sintetizzare le parte critiche di una applicazione in modo automatico.
Lay summary
 
Il progetto quindi si propone di avanzare lo stato dell'arte nell'identificazione e nella sintesi automatica di acceleratori.
Direct link to Lay Summary Last update: 21.10.2014

Responsible applicant and co-applicants

Employees

Publications

Publication
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code
Zacharopoulos Georgios, Ferretti Lorenzo, Giaquinta Emanuele, Ansaloni Giovanni, Pozzi Laura (2019), RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(4), 741-754.
Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors
Ferretti Lorenzo, Ansaloni Giovanni, Pozzi Laura, Aminifar Amir, Atienza David, Cammoun Leila, Ryvlin Philippe (2019), Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors, in 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, ItalyIEEE, Piscataway, New Jersey, United States.
Lattice-Traversing Design Space Exploration for High Level Synthesis
Ferretti Lorenzo, Ansaloni Giovanni, Pozzi Laura (2018), Lattice-Traversing Design Space Exploration for High Level Synthesis, in 2018 IEEE 36th International Conference on Computer Design (ICCD), Orlando, FL, USAIEEE, Piscataway, New Jersey, United States.
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis
Zacharopoulos Georgios, Barbon Andrea, Ansaloni Giovanni, Pozzi Laura (2018), Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis, in 2018 International Conference on High Performance Computing & Simulation (HPCS), Orleans, FranceIEEE, Piscataway, New Jersey, United States.
Circuit carving: A methodology for the design of approximate hardware
Scarabottolo Ilaria, Ansaloni Giovanni, Pozzi Laura (2018), Circuit carving: A methodology for the design of approximate hardware, in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, GermanyIEEE, Piscataway, New Jersey, United States.
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration
Ferretti Lorenzo, Ansaloni Giovanni, Pozzi Laura (2018), Cluster-Based Heuristic for High Level Synthesis Design Space Exploration, in IEEE Transactions on Emerging Topics in Computing, 1-1.
Data Reuse Analysis for Automated Synthesis of Custom Instructions in Sliding Window Applications.
ZacharopoulosGeorgios, AnsaloniGiovanni, PozziLaura (2017), Data Reuse Analysis for Automated Synthesis of Custom Instructions in Sliding Window Applications., in International Workshop on Polyhedral Compilation (IMPACT), Stockholm, Sweden HiPEAC, Gent, Belgium.
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.
ZacharopoulosGeorgios, FerrettiLorenzo, AnsaloniGiovanni, Di GuglielmoGiuseppe, CarloniLuca, PozziLaura, Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code., in International Conference on Computer Design (ICCD), Abu Dhabi, United Arab EmiratesIEEE, Piscataway, New Jersey, United States.

Collaboration

Group / person Country
Types of collaboration
Prof. Luca Carloni, Columbia University United States of America (North America)
- in-depth/constructive exchanges on approaches, methods or results
- Publication
- Exchange of personnel
Prof. Philip Brisk, UC Riverside United States of America (North America)
- in-depth/constructive exchanges on approaches, methods or results

Scientific events

Active participation

Title Type of contribution Title of article or contribution Date Place Persons involved
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE) Poster Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors. 25.03.2019 Firenze, Italy Ferretti Lorenzo; Ansaloni Giovanni;
IEEE International Conference on Computer Design (ICCD) Talk given at a conference Lattice-Traversing Design Space Exploration for High Level Synthesis. 07.10.2018 Orlando, FL, United States of America Ferretti Lorenzo;
IEEE International Conference on High Performance Computing and Simulation (HPCS) Talk given at a conference Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis. 16.07.2018 Orléans, France Zacharopoulos Georgios;
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE) Talk given at a conference Circuit carving: A methodology for the design of approximate hardware. 19.03.2018 Dresden, Germany Pozzi Laura;
IEEE International Conference on Computer Design (ICCD) Talk given at a conference Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. 05.11.2017 Boston, United States of America Ferretti Lorenzo; Ansaloni Giovanni;
HiPEAC International Workshop on Polyhedral Compilation Techniques (IMPACT) Talk given at a conference Data Reuse Analysis for Automated Synthesis of Custom Instructions in Sliding Window Applications. 23.01.2017 Stockholm, Sweden Zacharopoulos Georgios;


Associated projects

Number Title Start Funding scheme
182009 ML-edge: Enabling Machine-Learning-Based Health Monitoring in Edge Sensors via Architectural Customization 01.06.2019 Project funding (Div. I-III)
122158 Architectural design and exploration of innovative coarse grained reconfigurable arrays 01.10.2008 Project funding (Div. I-III)
113812 Compiler Technology for Customisable Embedded Processors 01.10.2006 Project funding (Div. I-III)
188613 ADApprox: Towards Application-Driven Approximate Logic Synthesis 01.10.2020 Project funding (Div. I-III)

Abstract

This project aims at enlarging the scope of automatic Instruction SetExtension (ISE). ISEs are special, complex instructions that are addedto a processor in order to make it better targeted to a particularapplication to be served, resulting in higher performance and betterpower efficiency. Automatic ISE is the process of devisingsuch extensions automatically from the application source code. Thestate of the art of automatic ISE indentification has advancedconsiderably in the past 15 years, including several papers by theapplicant. On the other hand, several challenges still lay ahead, andthe challenges here identified were inspired by reading a recentpaper, that set out to understand the sources ofinefficiencies of general-purpose processors, both in terms ofperformance and power. An important consideration is made at the endof the paper study: the only way to bridge the gap between swexecution, and dedicated hardware execution, is to specializethe baseline processor. The paper indeed adds more and more complexinstruction to a baseline processor under consideration, identifyingthese instructions manually and terming them 'magic' because oftheir complexity, and achieving some outstanding performanceimprovements. This proposal aims at identifying those sameinstructions, but in an automatic way; i.e., devisingalgorithms that can identify and synthesize those instructions withoutprogrammer intervention. The charachteristics that make theseinstructions special, and beyond the current challenges of state ofthe art tools, are: they cluster 100s of original operations into asingle instruction, they are tightly connected to custom data storageelements, they are built on top of vectorized code. These are indeedthe challenges that this proposal wants to tackle. This proposal aimstherefore at extending the state of the art in Instruction SetExtensions methodologies, combining them with compiler transformationssuch as vectorization, and finally analyzing the tradeoff of mappingsuch extensions on reconfigurable logic.
-