Reconfigurable Processors; Automatic Instruction Set Extensions; Customizable Processors; ASIPs; Accelerators; Heterogeneous Computing
Zacharopoulos Georgios, Ferretti Lorenzo, Giaquinta Emanuele, Ansaloni Giovanni, Pozzi Laura (2019), RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, 38(4), 741-754.
Ferretti Lorenzo, Ansaloni Giovanni, Pozzi Laura, Aminifar Amir, Atienza David, Cammoun Leila, Ryvlin Philippe (2019), Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors, in 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
, Florence, ItalyIEEE, Piscataway, New Jersey, United States.
Ferretti Lorenzo, Ansaloni Giovanni, Pozzi Laura (2018), Lattice-Traversing Design Space Exploration for High Level Synthesis, in 2018 IEEE 36th International Conference on Computer Design (ICCD)
, Orlando, FL, USAIEEE, Piscataway, New Jersey, United States.
Zacharopoulos Georgios, Barbon Andrea, Ansaloni Giovanni, Pozzi Laura (2018), Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis, in 2018 International Conference on High Performance Computing & Simulation (HPCS)
, Orleans, FranceIEEE, Piscataway, New Jersey, United States.
Scarabottolo Ilaria, Ansaloni Giovanni, Pozzi Laura (2018), Circuit carving: A methodology for the design of approximate hardware, in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
, Dresden, GermanyIEEE, Piscataway, New Jersey, United States.
Ferretti Lorenzo, Ansaloni Giovanni, Pozzi Laura (2018), Cluster-Based Heuristic for High Level Synthesis Design Space Exploration, in IEEE Transactions on Emerging Topics in Computing
ZacharopoulosGeorgios, AnsaloniGiovanni, PozziLaura (2017), Data Reuse Analysis for Automated Synthesis of Custom Instructions in Sliding Window Applications., in International Workshop on Polyhedral Compilation (IMPACT)
, Stockholm, Sweden HiPEAC, Gent, Belgium.
ZacharopoulosGeorgios, FerrettiLorenzo, AnsaloniGiovanni, Di GuglielmoGiuseppe, CarloniLuca, PozziLaura, Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code., in International Conference on Computer Design (ICCD)
, Abu Dhabi, United Arab EmiratesIEEE, Piscataway, New Jersey, United States.
This project aims at enlarging the scope of automatic Instruction SetExtension (ISE). ISEs are special, complex instructions that are addedto a processor in order to make it better targeted to a particularapplication to be served, resulting in higher performance and betterpower efficiency. Automatic ISE is the process of devisingsuch extensions automatically from the application source code. Thestate of the art of automatic ISE indentification has advancedconsiderably in the past 15 years, including several papers by theapplicant. On the other hand, several challenges still lay ahead, andthe challenges here identified were inspired by reading a recentpaper, that set out to understand the sources ofinefficiencies of general-purpose processors, both in terms ofperformance and power. An important consideration is made at the endof the paper study: the only way to bridge the gap between swexecution, and dedicated hardware execution, is to specializethe baseline processor. The paper indeed adds more and more complexinstruction to a baseline processor under consideration, identifyingthese instructions manually and terming them 'magic' because oftheir complexity, and achieving some outstanding performanceimprovements. This proposal aims at identifying those sameinstructions, but in an automatic way; i.e., devisingalgorithms that can identify and synthesize those instructions withoutprogrammer intervention. The charachteristics that make theseinstructions special, and beyond the current challenges of state ofthe art tools, are: they cluster 100s of original operations into asingle instruction, they are tightly connected to custom data storageelements, they are built on top of vectorized code. These are indeedthe challenges that this proposal wants to tackle. This proposal aimstherefore at extending the state of the art in Instruction SetExtensions methodologies, combining them with compiler transformationssuch as vectorization, and finally analyzing the tradeoff of mappingsuch extensions on reconfigurable logic.