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Design of Energy Efficient and Wireless Communication Systems under Unreliable Silicon

Applicant Burg Andreas Peter
Number 153640
Funding scheme Project funding (Div. I-III)
Research institution Laboratoire de circuits pour télécommunications EPFL - STI - IEL - TCL
Institution of higher education EPF Lausanne - EPFL
Main discipline Microelectronics. Optoelectronics
Start/End 01.02.2015 - 30.06.2018
Approved amount 192'463.00
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All Disciplines (2)

Discipline
Microelectronics. Optoelectronics
Electrical Engineering

Keywords (8)

Cross-Layer Hardware Design; Wireless Communication Systems; Variation Aware Design; Low Power Design; Memory Design; Quality Adaptive Systems; Voltage-Scaling; Approximate Computing

Lay Summary (German)

Lead
Die Mikroelektronik befindet sich zur Zeit an einem Scheidepunkt, da die Integration immer kleinerer Bauelemente es immer schwieriger macht zu garantieren, dass diese auch innerhalb vorgegebener Parameter funktionieren. Gleichzeitig steigen die Anforderungen an integrierte Schaltungen durch immer aufwaendiere Algorithmen und hoehere Datenraten. Dies ist insbesondere in der Mobilkommunikation ein Problem, deren Fortschritt von der Verfuegbarkeit hochintergrierter Schaltungen abhaengt und besonders in Bereich des Internet of Things nach immer stromsparenderen Loesungen verlangt.
Lay summary

Inhalt und Ziel des Forschungsprojekts

Ziel dieses Projektes ist die Entwicklung neuer Methoden fuer den Entwurf integrierter Schaltungen fuer die Mobilkommunikation in zukuenftigen Prozesstechnologien. Im speziellen beschaeftigen wir uns mit dem wachsenden Problem der Zuverlaessigkeit der verwendeten Halbleiterbauelemente die gegenwaertig dem weiteren Fortschritt bei der Verringerung des Stromverbrauchs von Endgeraeten im Wege steht. Mit einem neuen Designansatz (oft auch bekannt als "Approximate Computing" oder "Computing on Unreliable Silicon") versuchen wir kleinere und stromsparendere Schaltungen zu entwerfen indem wir die die inherente Fehlertleraz eines Kommunikationssystems bei der Entwicklung beruecksichtigen. Wir hoffen mit diesem Ansatz auf aufwaendige und teure Massnahmen verzichten zu koennen die ansonsten notwendig waeren um selbst kleinste Fehler in der Hardware zu vermeiden. Die Herausforderung besteht nun darin, dafuer zu sorgen, dass die Auswirkungen moeglicher Fehler ausschliesslich gering ist, so dass sie die Qualitaet des Systems (z.B. die Uebertragungsrate) nur marginal beeintraechtigen.

Wissenschaftlicher und gesellschaftlicher Kontext des Forschungsprojekts

Wir erwarten dass unsere Forschung dazu beitraegt eine neues Paradigma zum Entwurf integrierter Schaltungen zu etablieren das stromsparendere and schnellere Mikroelektronik ermoeglicht. Waehrend wir uns in diesem Projekt auf die Mobilkommunikation konzentrieren, erwarten wir dass aehnliche Konzepte auf viele andere Probleme und im Bereichen des Internet of Things angewendet werden koennen.

Direct link to Lay Summary Last update: 23.03.2015

Responsible applicant and co-applicants

Employees

Publications

Publication
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing
Ghanaatian Reza, Balatsoukas-Stimming Alexios, Muller Thomas Christoph, Meidlinger Michael, Matz Gerald, Teman Adam, Burg Andreas (2018), A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(2), 329-340.
DVFS based power management for LDPC decoders with early termination
Ghanaatian Reza, Burg Andreas (2017), DVFS based power management for LDPC decoders with early termination, in 2017 IEEE International Workshop on Signal Processing Systems (SiPS), LorientIEEE, France.
A low-power correlator for wakeup receivers with algorithm pruning through early termination
Ghanaatian Reza, Whatmough Paul N., Constantin Jeremy, Teman Adam, Burg Andreas (2016), A low-power correlator for wakeup receivers with algorithm pruning through early termination, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montréal, QC, CanadaIEEE, Canada.
A fully-unrolled LDPC decoder based on quantized message passing
Balatsoukas-Stimming Alexios, Meidlinger Michael, Ghanaatian Reza, Matz Gerald, Burg Andreas (2015), A fully-unrolled LDPC decoder based on quantized message passing, in 2015 IEEE Workshop on Signal Processing Systems (SiPS), Hangzhou, ChinaIEEE, USA.

Collaboration

Group / person Country
Types of collaboration
Integrated Systems Laboratory/ ETH Zurich Switzerland (Europe)
- in-depth/constructive exchanges on approaches, methods or results
- Publication
- Exchange of personnel
Embedded Systems Laboratory Switzerland (Europe)
- in-depth/constructive exchanges on approaches, methods or results
- Publication
- Exchange of personnel
Nanoelectronics Research Lab/Purdue University United States of America (North America)
- in-depth/constructive exchanges on approaches, methods or results
Institute for Communication Technologies and Embedded Systems/ RWTH Aachen University Germany (Europe)
- in-depth/constructive exchanges on approaches, methods or results
- Publication
- Exchange of personnel
TU-Vienna Austria (Europe)
- in-depth/constructive exchanges on approaches, methods or results
- Publication

Scientific events

Active participation

Title Type of contribution Title of article or contribution Date Place Persons involved
ARM Research Summit Poster LoRa Modem Implementation as a Proof of Concept for a Flexible IoT Platform Solution 17.09.2018 Cambridge, UK, Great Britain and Northern Ireland Burg Andreas Peter; Ghanaatian Jahromi Reza;


Communication with the public

Communication Title Media Place Year
New media (web, blogs, podcasts, news feeds etc.) Unleashing Finite-Alphabet Implementations of LDPC Decoders International 2018

Associated projects

Number Title Start Funding scheme
119057 Circuits and Systems for Next Generation Wireless Communication 01.01.2009 SNSF Professorships

Abstract

Although aggressive CMOS technology scaling into the nanometer regime has allowed for the realization of complex high performance systems, unfortunately it has also led to process variation, especially in sub-22 nm geometries, that lead to transient and permanent timing and memory failures threatening the correct functionality of future systems. Currently, manufacturers go to great lengths to guarantee fault-free operation of their products by introducing redundancy in voltage margins, conservative layout rules, and extra protection circuitry measures which unfortunately lead to power increase conflicting with the other main design challenge in nanometer nodes and portable devices of low power operation. Unfortunately, such energy overheads cannot be alleviated easily even by lowering supply voltage below a nominal value which is considered as one of the most effective power reduction methods. Nonetheless, based on the current design trends, the worsening of variability in scaled nodes will soon force manufacturers to increase the protection mechanisms which will have as a result the further increase of power and cost and sub-optimal exploitation of silicon real-estate. Based on such facts, latest ITRS trends predict that in order to continue the technology scaling and design evolution there is need for a shift beyond the 100% error-free design paradigm in which it is impossible not to accept unreliable computation and storage. Several approaches have shown recently the potential of such a paradigm shift in saving considerable amounts of energy and cost in various probabilistic applications such as multimedia and data mining applications, but there is still a need i) to explore the inherent resilience of many other applications and ii) capture systematically the interplay between energy, reliability, and quality as well as promote energy-awareness across different abstraction layers to exploit scalability at the system level for energy efficiency. In this project we plan to develop the above described concepts and ideas for wireless communication systems. To this end, we propose to exploit their inherent error resilience by devising mechanisms on various levels of design abstraction that allow the system to adapt gracefully to dynamically changing operating conditions, user requirements, and to variations in the manufacturing process without the need for costly design margins. We believe that wireless systems are an excellent test vehicle for the application of these new ideas since they i) naturally deal with signals that are already corrupted by noise and ii) are scalable and probabilistic, i.e., consist of algorithms that try to decode the received bits by trading the accuracy of computations and number of operations for power reduction and throughput improvement. A cross-layer design methodology that i) exploits the resilience limits of communication systems as means of increasing manufacturing yield, device lifetime, and energy efficiency at no cost and ii) provides mechanisms at various levels of design abstraction to exploit the inherent scalability of communication algorithms for further improving those limits and the associated cost metrics (energy efficiency, reliability, yield) is envisioned to lead to uniquely optimal designs. In this proposal, reliability issues are therefore not seen as a problem, but rather as an opportunity to rethink computation in a novel way to put scalability and inherent error resilience to service. In case of high defect rates, rather than trying to correct all errors, the proposed approach applies unequal error protection at various system layers, giving priority to the protection of the most significant blocks/computations in the overall system. Less critical parts are allowed to fail (partially), to provide erroneous results, or to be skipped as long as an acceptable quality of service is maintained. Overall, the proposed solutions and the degree of energy efficiency that can be achieved by them will indicate the characteristics (on system, algorithm, and circuit/architecture layers) that need to be adopted by future wireless transceivers which are at the heart of all mobile devices. Therefore, the proposed project will contribute to the evolution of future mobile platforms ensuring the improvement of everyday life and helping Switzerland to strengthen its research in one of the most critical issues that semiconductor industry is facing today.
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