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Exploration of Negative Capacitance Ferroelectric Device Concepts and Technologies

English title Exploration of Negative Capacitance Ferroelectric Device Concepts and Technologies
Applicant Ionescu Mihai Adrian
Number 149495
Funding scheme Project funding
Research institution Laboratoire des dispositifs nanoélectroniques EPFL - STI - IEL - NANOLAB
Institution of higher education EPF Lausanne - EPFL
Main discipline Microelectronics. Optoelectronics
Start/End 01.11.2013 - 31.10.2017
Approved amount 815'600.00
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All Disciplines (2)

Discipline
Microelectronics. Optoelectronics
Material Sciences

Keywords (6)

nanotechnology; flexible substrate technologies; ferroelectric material; negative capacitance effect; subthermal switch; low voltage ferroelectric memory

Lay Summary (French)

Lead
In this proposal we will explore novel devices and technologies based on the concept of negative capacitance, that serve as alternatives for low power low voltage digital circuits and memories, exploiting ferroelectric gate stacks on silicon and/or on flexible substrates.
Lay summary

Ce projet de recherche est dédié à l’exploration des nouveaux composants et technologies basés sur le concept de capacité négative qui peut être exploitée pour réduire la tension d’alimentation et la consommation des circuits logiques et des mémoires. Comme principe on va exploiter une amplification interne de la tension de grille, par le gate stack lui-même, ce qui n’est pas possible actuellement dans tout transistor avancé.

Plus particulièrement on va investiguer des structures ferroélectriques qui peuvent servir comme diélectrique de grilles des transistors MOSFET. La recherche serra structuré à deux niveaux (1) dispositifs ferroélectrique sur substrat de silicium massif, pour applications jusqu’à 1GHZ, (2) des composants ferroélectriques sur substrat flexible (Kapton) pour des tags RF.

Le projet réunit cinq groupes de recherche : 2 de l’EPFL (Ionescu et Setter) et 3 de ETH Zürich (Tröester, Schek et Luisier) et une collaboration avec IBM Research Zürich.

Direct link to Lay Summary Last update: 28.09.2013

Responsible applicant and co-applicants

Employees

Publications

Publication
Effect of Hysteretic and non-Hysteretic Negative Capacitance on Tunnel FETs DC Performance
Saeidi Ali, Jazaeri Farzan, Stolichnov Igor, Luong Gia V, Zhao Qing-Tai, Mantl Siegfried, Ionescu Adrian M (2018), Effect of Hysteretic and non-Hysteretic Negative Capacitance on Tunnel FETs DC Performance, in accepted on Nanotechnology.
Charge Trapping Mechanism Leading to Sub-60-mV/decade-Swing FETs
Daus Alwin, Vogt Christian, Münzenrieder Niko, Petti Luisa, Knobelspies Stefan, Cantarella Giuseppe, Luisier Mathieu, Salvatore Giovanni A., Tröster Gerhard (2017), Charge Trapping Mechanism Leading to Sub-60-mV/decade-Swing FETs, in IEEE Transactions on Electron Devices , 64, 2789.
Ferroelectric‐Like Charge Trapping Thin‐Film Transistors and Their Evaluation as Memories and Synaptic Devices
Daus Alwin, Lenarczyk Pawel, Petti Luisa, Münzenrieder Niko, Knobelspies Stefan, Cantarella Giuseppe, Vogt Christian, Salvatore Giovanni A., Luisier Mathieu, Tröster Gerhard (2017), Ferroelectric‐Like Charge Trapping Thin‐Film Transistors and Their Evaluation as Memories and Synaptic Devices, in Advanced Electronic Materials, 1700309.
Flexible CMOS electronics based on p-type Ge2Sb2Te5 and n-type InGaZnO4 semiconductors
Daus Alwin, Han S., Knobelspies Stefan, Cantarella Giuseppe, Vogt Christian, Münzenrieder Niko, Tröster Gerhard (2017), Flexible CMOS electronics based on p-type Ge2Sb2Te5 and n-type InGaZnO4 semiconductors, in IEEE International Electron Devices Meeting (IEDM), San Francisco, USIEEE conference proceeding, San Francisco, US.
Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study
Saeidi Ali, Jazaeri Farzan, Bellando Francesco, Stolichnov Igor, Luong Gia V, Zhao Qing-Tai, Mantl Siegfried, Enz Christian C, Ionescu Adrian M (2017), Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study, in IEEE Electron Device Letters, 38(10), 1485-1488.
Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation
Saeidi Ali, Jazaeri Farzan, Bellando Francesco, Stolichnov Igor, Enz Christian C, Ionescu Adrian M (2017), Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation, in Solid-State Device Research Conference (ESSDERC), 2017 47th European, 78-81, IEEE conference proceeding, Leuven, Belgium78-81.
Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing
Saeidi Ali, Jazaeri Farzan, Stolichnov Igor, Luong Gia Vinh, Zhao Qing-Tai, Mantl Siegfried, Ionescu Adrian M (2017), Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing, in Silicon Nanoelectronic Workshop, (EPFL-CONF-), IEEE conference proceeding, Kyoto, Japan(EPFL-CONF-).
Physical modeling of ferroelectric field-effect transistors in the negative capacitance regime
P. Lenarczyk and M. Luisier (2016), Physical modeling of ferroelectric field-effect transistors in the negative capacitance regime, in Int. Conf. Sim. of Semicond. Proc. Dev. (SISPAD), 2016, Germany, 2016IEEE, USA.
Condition for the negative capacitance effect in metal--ferroelectric--insulator--semiconductor devices
Rusu Alexandru, Saeidi Ali, Ionescu Adrian M (2016), Condition for the negative capacitance effect in metal--ferroelectric--insulator--semiconductor devices, in Nanotechnology, 27(11), 115201-115201.
Double-gate negative-capacitance MOSFET with PZT gate-stack on ultra thin body SOI: An experimentally calibrated simulation study of device performance
Saeidi Ali, Jazaeri Farzan, Stolichnov Igor, Ionescu Adrian M (2016), Double-gate negative-capacitance MOSFET with PZT gate-stack on ultra thin body SOI: An experimentally calibrated simulation study of device performance, in IEEE Transactions on Electron Devices, 63(12), 4678-4684.
Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric
Saeidi A, Biswas A, Ionescu Adrian M (2016), Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric, in Solid-State Electronics, 124, 16-23.
Positive charge trapping phenomenon in n-channel thin-film transistors with amorphous alumina gate insulators
Daus Alwin, Vogt Christian, Münzenrieder Niko, Petti Luisa, Knobelspies Stefan, Cantarella Giuseppe, Luisier Mathieu, Salvatore Giovanni A., Tröster Gerhard (2016), Positive charge trapping phenomenon in n-channel thin-film transistors with amorphous alumina gate insulators, in Journal of Applied Physics , 120, 244501.
Design Considerations of Ferroelectric Properties for Negative Capacitance MOSFETs
Saeidi Ali, Jazaeri Farzan, Stolichnov Igor, Enz Christian C, Ionescu Adrian M, Design Considerations of Ferroelectric Properties for Negative Capacitance MOSFETs, in accepted on Electron Devices Technology and Manufacturing conference 2018.

Collaboration

Group / person Country
Types of collaboration
IBM Research GmbH Switzerland (Europe)
- Publication
- Exchange of personnel
- Industry/business/other use-inspired collaboration

Scientific events

Active participation

Title Type of contribution Title of article or contribution Date Place Persons involved
EDMI (Doctoral Program in Microsystems and Microelectronics) research day 2017 Individual talk Exploration of Negative Capacitance Devices and Technologies 14.12.2017 Lausanne, Switzerland Saeidi Ali;
IEEE International Electron Devices Meeting (IEDM) Talk given at a conference Flexible CMOS electronics based on p-type Ge2Sb2Te5 and n-type InGaZnO4 semiconductors 04.12.2017 San Francisco, United States of America Daus Alwin; Tröster Gerhard;
Swiss E-Print Poster Flexible synaptic thin-film transistors on plastic for neuromorphic computing applications 26.09.2017 Basel, Switzerland Daus Alwin; Tröster Gerhard;
47th European Solid-State Device Research Conference (ESSDERC-ESSCIRC) 2017 Talk given at a conference Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation 11.09.2017 Leuven, Belgium Saeidi Ali; Ionescu Mihai Adrian;
Silicon Nanoelectronics Workshop 2017 Talk given at a conference Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing 04.06.2017 Kyoto, Japan Saeidi Ali; Ionescu Mihai Adrian;
CMI (Center of micronanotechnology at EPFL) annual meeting 2017 Poster Experimental Based Simulation of Negative Capacitance MOSFETs 02.05.2017 Lausanne, Switzerland Saeidi Ali;
International Thin-Film Transistor Conference (ITC) Talk given at a conference Flexible Ferroelectric/Moving-Charge IGZO TFT Memory based on BaTiO3-PVA Nanocomposites 23.02.2017 Austin, Texas, United States of America Tröster Gerhard; Daus Alwin;
2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Talk given at a conference Physical modeling of ferroelectric field-effect transistors in the negative capacitance regime 06.09.2016 Nuremberg, Germany Lenarzcyk Pawel; Luisier Mathieu;
MaP Graduate Symposium Poster Charge trapping for ultra-low power electronics beyond conventional limits 09.06.2016 Zürich, Switzerland Tröster Gerhard; Daus Alwin;
International Thin-Film Transistor Conference (ITC), Poster Low-voltage flexible memory thin-film transistor based on charge generation from Fowler-Nordheim tunnel stress 25.02.2016 Hsinchu, Taiwan Daus Alwin; Tröster Gerhard;


Awards

Title Year
Best poster award at Swiss e-print conference 2017
Best student paper award at International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2016) 2016

Associated projects

Number Title Start Funding scheme
159314 Physics-based Modeling of Electronic Devices at the Nanometer Scale 01.08.2015 SNSF Professorships

Abstract

In this proposal we will explore novel devices and technologies based on the concept of negative capacitance, that serve as alternatives for low power low voltage digital circuits and memories, exploiting ferroelectric gate stacks on silicon and/or on flexible substrates. We focus the proposed research on two levels, corresponding to the potential applications of the new negative capacitance (NC) devices: (i) NC ferroelectric devices on bulk silicon, targeting low power applications operating below 1GHz and (ii) NC ferroelectric devices on flexible substrates (Kapton) targeting 13MHz passive RFID tags.
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