share-nothing; transaction processing; data sharing workload-aware processing; thread migration; share-everything; data management; instruction cache; data partitioning; hardware-aware processing
Appuswamy Raja, Anadiotis Angelos C., Porobic Danica, Iman Mustafa K., Ailamaki Anastasia (2017), Analyzing the impact of system architecture on the scalability of OLTP engines for high-contention workloads, in
Proceedings of the VLDB Endowment, 11(2), 121-134.
Sirin Utku, Yasin Ahmad, Ailamaki Anastasia (2017), A methodology for OLTP micro-architectural analysis, in
the 13th International Workshop, Chicago, IllinoisACM New York, NY, USA ©2016, New York, NY, USA ©2016.
Appuswamy Raja (2017), The Case For Heterogeneous HTAP, in
8th Biennial Conference on Innovative Data Systems Research, Chaminade, California, January 8-11,201CIDR Conference, USA.
Porobic Danica, Pandis Ippokratis, Branco Miguel, Tözün Pınar, Ailamaki Anastasia (2016), Characterization of the Impact of Hardware Islands on OLTP, in
The VLDB Journal, 25(5), 625-650.
Porobic Danica, Tözün Pınar, Appuswamy Raja, Ailamaki Anastasia (2016), More than a networkdistributed OLTP on clusters of hardware islands, in
the 12th International Workshop, San Francisco, CaliforniaACM New York, NY, USA ©2016, New York, NY, USA ©2016.
Sirin Utku, Tözün Pinar, Porobic Danica, Ailamaki Anastasia (2016), Micro-architectural Analysis of In-memory OLTP, in
the 2016 International Conference, San Francisco, California, USAACM New York, NY, USA ©2016, New York, NY, USA ©2016.
Sirin Utku, Appuswamy Raja, Ailamaki Anastasia (2016), OLTP on a server-grade ARMpower, throughput and latency comparison, in
the 12th International Workshop, San Francisco, CaliforniaACM New York, NY, USA ©2016, New York, NY, USA ©2016.
Psaroudakis Iraklis, Kissinger Thomas, Porobic Danica, Ilsche Thomas, Liarou Erietta, Tözün Pınar, Ailamaki Anastasia, Lehner Wolfgang (2014), Dynamic fine-grained scheduling for energy-efficient main-memory queries, in
the Tenth International Workshop, Snowbird, UtahACM New York, NY, USA ©2016, New York, NY, USA ©2016.
Porobic Danica, Liarou Erietta, Tozun Pinar, Ailamaki Anastasia (2014), ATraPos: Adaptive Transaction Processing on Hardware Islands, in
ICDE 2014, 30th ICDE Chicago, IL, USANA, NA.
Transaction processing (TP) is a multi-billion dollar industry, as it is mission-critical for enterprises with little margin for compromising either performance or scalability. Major database vendors spend significant effort in developing highly-optimized TP software releases, often with platform-specific optimizations. Over the past few decades, TP has benefited greatly by the ever-increasing uniprocessor speed - until 2004, when the frequency-scaling wall forced that trend to a screeching halt. Nowadays, faster hardware means more processing cores in each CPU chip, forming chip multiprocessors (multicore or CMP), and servers with multiple CPU sockets of multicore processors (SMP of CMP). CMP are highly parallel and heterogeneous in communication costs: sets, or islands, of processing cores communicate with each other efficiently through common on-chip caches, but communicate less efficiently with others through bandwidth-limited and higher-latency links. Even though CMP dominate in modern data-centers, TP engine architecture is oblivious to non-uniform memory access costs across computing cores, so transactional workloads exhibit suboptimal and even worse, unpredictable performance. Therefore, every new release of hardware platform is followed by a humongous investment by database companies to make their systems scale to decent performance.Recent research efforts to improve TP scalability on CMP considers data organization, sometimes combined with clever work assignment, following either a shared-nothing or a shared-memory principle. Others propose modular engine architectures and grouped query execution for performance. We identify the root cause for inefficient execution of transactional workloads on CMP to be that typical TP engines partition data and schedule their work independently of the specifics of either the workload or the hardware. Our proposal builds on the state-of-the-art by developing a complete infrastructure of techniques inspired synergistically by data, work, and hardware design considerations. The proposed work carefully balances partitioning and sharing of data and instructions, through (a) partitioning data structures across islands of communication, (b) dynamic work assignment and thread migration, and (c) novel operators, enacted by sharing opportunities. We will develop these techniques in parallel due to synergies but also potential conflicts and tradeoffs in the techniques (e.g. instruction and data co-locality).The ambition of this proposal is to lay the groundwork for database systems that adapt and reconfigure online, depending on the workload and the hardware, while ensuring efficient resource utilization. Our research results will directly impact multiple sectors of society that rely on transaction processing for their business processes (e.g. finance, accounting, e-commerce, healthcare), many of which are a significant part of the Swiss industrial sector.