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Architectural design and exploration of innovative coarse grained reconfigurable arrays

English title Architectural design and exploration of innovative coarse grained reconfigurable arrays
Applicant Pozzi Laura
Number 122158
Funding scheme Project funding (Div. I-III)
Research institution Istituto di sistemi informatici (SYS) Facoltà di scienze informatiche
Institution of higher education Università della Svizzera italiana - USI
Main discipline Information Technology
Start/End 01.10.2008 - 31.08.2011
Approved amount 151'763.00
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Keywords (2)

coarse-grained reconfigurable arrays (CGRAs); architectural exploration

Lay Summary (English)

Lead
Lay summary
Reconfigurable Arrays combine the benefit of spatial execution, typical of hardware solutions, with that of programmability, present in microprocessors. As such, they could represent an efficient alternative to hardwired logic for implementing embedded applications, since they can provide hw acceleration without making the engineer commit to a non-modifiable design.Unfortunately, other drawbacks have kept reconfigurable logic from becoming a largely adopted solution in the high performance embedded field; among different factors, the performance and area gap that still exists with hardwired logic is certainly one of the most important.The problem of bridging this gap has been the focus of much research in the last decades, and a number of advancements have been made; in particular, Coarse Grain Reconfigurable Architectures (CGRAs) have been proposed in order to overcome the shortcomings of fine grain solutions such as FPGAs (Field Programmable Gate Arrays). CGRAs exhibit a larger cell granularity, therefore proving less flexible, but more efficient for arithmetic computations.This proposal aims at developing an innovative CGRA architecture that has the potential of providing an additional step in the direction of decreasing the above-mentioned gap further. There are two main reasons indicating that the proposed research has the potential of advancing the state of the art in CGRAs. The first point is that an innovative cell structure is envisioned, that is composed of a multiplicity of ALUs, flexibly connected, as opposed to a single ALU as is the case of most previous work. This feature enables the mapping of entire arithmetic/logic expressions, as opposed to single operations, onto one cell, and has the potential of providing enhanced area and delay results to the state of the art.The second important point is the presence of an exploration level in the proposed methodology. Having noticed that past works lack a systematic way of analysing and evaluating architectural choices, here, instead, architectural exploration of various parametric cell granularity and routing topologies is envisioned, enabled by retargetable compilation technology capable of mapping custom instructions onto different architectures. This makes it possible to study the effectiveness of different architectural choices in a systematic way.An initial study has been carried out by the proposer and by her PhD student---for whom this grant is requested---during the last 5 months, and has provided encouraging results.
Direct link to Lay Summary Last update: 21.02.2013

Responsible applicant and co-applicants

Employees

Publications

Publication
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays
G. Ansaloni K. Tanimura L. Pozzi and N. Dutt (2012), Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(12), 1803-1816.
EGRA: a Coarse Grained Reconfigurable Architectural Template
Giovanni Ansaloni Paolo Bonzini and Laura Pozzi (2011), EGRA: a Coarse Grained Reconfigurable Architectural Template, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(19), 1062-1074.
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays
G. Ansaloni K. Tanimura L. Pozzi and N. Dutt (2011), Slack-aware scheduling on Coarse Grained Reconfigurable Arrays, in Design Automation and Test in Europe (DATE), IEEE, DATE.
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
G. Ansaloni P. Bonzini and L. Pozzi (2009), Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration, in Design Automation and Test in Europe (DATE) Conference, IEEE, DATE.
Compiling custom instructions onto expression-grained reconfigurable architectures
P. Bonzini G. Ansaloni and L. Pozzi (2008), Compiling custom instructions onto expression-grained reconfigurable architectures, in International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), IEEE, USA.
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays
G. Ansaloni P. Bonzini and L. Pozzi (2008), Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays, in Symposium on Application Specific Processors (SASP), IEEE, Anaheim, California.

Associated projects

Number Title Start Funding scheme
156397 Magic ISEs: Enlarging the Scope of Automatic Instruction Set Extension 01.11.2014 Project funding (Div. I-III)

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