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Full-Wafer Dynamic Nanostencil Lithography

English title Full-Wafer Dynamic Nanostencil Lithography
Applicant Savu Veronica
Number 121923
Funding scheme Ambizione
Research institution Laboratoire de microsystèmes 1 EPFL - STI - IMT - LMIS1
Institution of higher education EPF Lausanne - EPFL
Main discipline Material Sciences
Start/End 01.12.2008 - 30.11.2011
Approved amount 450'185.00
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All Disciplines (4)

Discipline
Material Sciences
Condensed Matter Physics
Microelectronics. Optoelectronics
Other disciplines of Engineering Sciences

Keywords (3)

stencil lithography; shadow mask; dynamic stencil

Lay Summary (English)

Lead
Lay summary
Today's technological goal can be summarized in three words: smaller, faster, and cheaper. Not only can stencil lithography (SL) provide major advantages in all three domains, but it can also open completely new paths in the field of nanofabrication. The standard way of fabricating micro and nanodevices involves spinning a polymer layer on top of a Si wafer, exposing parts of it to radiation, and removing the resist parts which have been exposed by dipping the wafer in a chemical solution. SL is a resist-less technique which can integrate patterning in one step at micro- and nano-scales. It consists of selectively depositing and etching material through a stencil (membrane with apertures) located in close proximity to a substrate. At the end of the process, the aperture pattern in the stencil is transferred into the substrate, the stencil can be removed, and the substrate wafer is ready for the next processing step.

Although the technique is quick and clean, several challenges remain to be addressed. When the thickness of the deposited material is comparable to the aperture size, the apertures can become clogged due to the adhesion of material on their side walls. Another important aspect of SL is blurring, i.e. the distortion of the pattern when transferred from stencil to substrate. This phenomenon depends on the setup geometry and on the material itself.

Some of SL's unique applications include: 3D nanopatterning (AFM tip patterning, NEMS on CMOS, microlens nanopatterning), depositing "un-conventional" (e.g. organic) materials on "un-conventional" substrates (e.g. PDMS, PET, polymide, functionalized surfaces), and the easy creation of customized prototypes via dynamic SL (one can "write" any arbitrary pattern with the material deposited through a hole in a membrane, while the stencil trajectory follows the desired path).

The goal of this proposed research is exploring the limits imposed by clogging and blurring on nanostencil lithography, culminating with the development of a "self-cleaning" nanostencil, which allow in-situ multi-layer multi-pattern surface structuring using (quasi)dynamic SL.
Direct link to Lay Summary Last update: 21.02.2013

Responsible applicant and co-applicants

Employees

Publications

Publication
Compliant membranes improve resolution in full-wafer micro/nanostencil lithography.
Sidler Katrin, Villanueva Luis G, Vazquez-Mena Oscar, Savu Veronica, Brugger Juergen (2012), Compliant membranes improve resolution in full-wafer micro/nanostencil lithography., in Nanoscale, 4(3), 773-8.
100 mm dynamic stencils pattern sub-micrometre structures
Savu V, Xie SQ, Brugger J (2011), 100 mm dynamic stencils pattern sub-micrometre structures, in NANOSCALE, 3(7), 2739-2742.
Ambipolar silicon nanowire FETs with stenciled-deposited metal gate
Sacchetto D, Savu V, De Micheli G, Brugger J, Leblebici Y (2011), Ambipolar silicon nanowire FETs with stenciled-deposited metal gate, in MICROELECTRONIC ENGINEERING, 88(8), 2732-2735.
Robust PECVD SiC membrane made for stencil lithography
Xie SQ, Savu V, Tang W, Vazquez-Mena O, Sidler K, Zhang HX, Brugger J (2011), Robust PECVD SiC membrane made for stencil lithography, in MICROELECTRONIC ENGINEERING, 88(8), 2790-2793.
Three-level stencil alignment fabrication of a high-k gate stack organic thin film transistor
Cvetkovic NV, Sidler K, Savu V, Brugger J, Tsamados D, Ionescu AM (2011), Three-level stencil alignment fabrication of a high-k gate stack organic thin film transistor, in MICROELECTRONIC ENGINEERING, 88(8), 2496-2499.
Heated membranes prevent clogging of apertures in nanostencil lithography
Xie S. Q., Savu V., Brugger J. (2011), Heated membranes prevent clogging of apertures in nanostencil lithography, in Proceedings of Transducers 2011, 998-1001.
High Throughput Nanofabrication of Silicon Nanowire and Carbon Nanotube Tips on AFM Probes by Stencil-Deposited Catalysts
Engstrom DS, Savu V, Zhu XN, Bu IYY, Milne WI, Brugger J, Boggild P (2011), High Throughput Nanofabrication of Silicon Nanowire and Carbon Nanotube Tips on AFM Probes by Stencil-Deposited Catalysts, in NANO LETTERS, 11(4), 1568-1574.
Reliable and Improved Nanoscale Stencil Lithography by Membrane Stabilization, Blurring, and Clogging Corrections
Vazquez-Mena O, Sidler K, Savu V, Park CW, Villanueva LG, Brugger J (2011), Reliable and Improved Nanoscale Stencil Lithography by Membrane Stabilization, Blurring, and Clogging Corrections, in IEEE TRANSACTIONS ON NANOTECHNOLOGY, 10(2), 352-357.
SiN membranes with submicrometer hole arrays patterned by wafer-scale nanosphere lithography
Klein MJK, Montagne F, Blondiaux N, Vazquez-Mena O, Heinzelmann H, Pugin R, Brugger J, Savu V (2011), SiN membranes with submicrometer hole arrays patterned by wafer-scale nanosphere lithography, in JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 29(2), 1-5.
The effects of channel length and film microstructure on the performance of pentacene transistors
Fleischli FD, Sidler K, Schaer M, Savu V, Brugger J, Zuppiroli L (2011), The effects of channel length and film microstructure on the performance of pentacene transistors, in ORGANIC ELECTRONICS, 12(2), 336-340.

Scientific events

Active participation

Title Type of contribution Title of article or contribution Date Place Persons involved
Swiss Nanoconvention 18.05.2011 Baden


Knowledge transfer events

Active participation

Title Type of contribution Date Place Persons involved
Environnement Professionnel Microtechnologies (EPMT) 24.05.2011 Lausanne, Switzerland


Communication with the public

Communication Title Media Place Year
New media (web, blogs, podcasts, news feeds etc.) A faster, cheaper method for making transistors and chips EPFL News Western Switzerland 26.09.2011
New media (web, blogs, podcasts, news feeds etc.) Advances in nanostencil lithography SPIE Newsroom International 10.03.2011

Awards

Title Year
Honorable Mention for Optical Image at EIPBN conference 2011

Associated projects

Number Title Start Funding scheme
139505 Nanostencil Lithography: Perfecting the Tool towards Selected Applications 01.02.2012 Ambizione
139505 Nanostencil Lithography: Perfecting the Tool towards Selected Applications 01.02.2012 Ambizione

Abstract

Today’s technological goal can be summarized in three words: smaller, faster, cheaper. Not only can stencil lithography (SL) provide major advantages in all three domains, but it can also open completely new paths in the field of nanofabrication. SL is a resistless technique which can integrate patterning in one step at micro- and nano-scales. It consists of selectively depositing and etching material through a stencil (membrane with apertures) located in close proximity to a substrate. At the end of the process, the aperture pattern in the stencil is transferred into the substrate, the stencil can be removed, and the substrate wafer is ready for the next processing step.Although the technique is quick and clean, several challenges remain to be addressed. When the thickness of the deposited material is comparable to the aperture size, the apertures can become clogged due to the adhesion of material on their side walls. In the case of static SL (the stencil is clamped to the substrate, used once, and then removed), the stencil can be unclogged (using e.g. wet etching) and reused, increasing the cost-efficiency of this technique. In the case of (quasi)dynamic SL (the stencil is moved w.r.t. the substrate for in-situ consecutive depositions of different materials and different patterns from the same stencil), clogging becomes the bottleneck, limiting the total amount of deposited material. Another important aspect of SL is blurring, i.e. the distortion of the pattern when transferred from stencil to substrate. This phenomenon depends on the setup geometry and on the material itself.Some of SL’s unique applications include: 3D nanopatterning (AFM tip patterning, NEMS on CMOS, microlens nanopatterning), depositing “un-conventional” (e.g. organic) materials on “un-conventional” substrates (e.g. PDMS, PET, polymide, functionalized surfaces), and the easy creation of customized prototypes via dynamic SL (one can “write” any arbitrary pattern with the material deposited through a hole in a membrane, while the stencil trajectory follows the desired path).The goal of this proposed research is exploring the limits imposed by clogging and blurring on nanostencil lithography, culminating with the development of a “self-cleaning” nanostencil, which allow in-situ multi-layer multi-pattern surface structuring using (quasi)dynamic SL. The chronological research structure will be centered around the following tasks: •Push the stencil present resolution limit to under 50 nm (use thinner membranes, develop new patterning process with e-beam step on top of released membrane)•Implement electrostatic chuck for less pattern distortion (due to blurring)•Characterize nanostencil clogging for static and dynamic SL vs. material, stencil speed, etc.•Evaluate the slow-down of the clogging of nanoapertures when using SAM-coated stencils•develop new high-melting point membrane material (e.g. SiC), more heat-resistant•integrate new membrane with conducting wires used as on-membrane heating elements•characterize nanoaperture unclogging using in-situ local heating of the membranes through the heating element, by re-evaporating the clogging material off the stencil•install stage temperature control unit•fabricate novel structures (films and wires) and devices (junctions, organic transistors) As part of one of the world’s leading research groups in dynamic stencil lithography, I see this research as the next necessary step for the advancement of the field. In-situ “self cleaning” nanostencils will pave the way to the efficient, in-parallel, clean fabrication of complex, novel, locally functionalized devices.
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