Project

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Circuits and Systems for Next Generation Wireless Communication

English title Circuits and Systems for Next Generation Wireless Communication
Applicant Burg Andreas Peter
Number 119057
Funding scheme SNSF Professorships
Research institution Laboratoire des télécommunications EPFL - STI - IEL - TCOM
Institution of higher education EPF Lausanne - EPFL
Main discipline Microelectronics. Optoelectronics
Start/End 01.01.2009 - 28.02.2013
Approved amount 1'173'001.00
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All Disciplines (2)

Discipline
Microelectronics. Optoelectronics
Electrical Engineering

Keywords (9)

Wireless communication; MIMO; VLSI; deep sub-micron; circuits; MP-SoC; low power; communications; signal processing

Lay Summary (English)

Lead
Lay summary
Summary:
Next generation wireless communication systems rely on new algorithms and transmission schemes to deliver high data rates to a growing number of users. Unfortunately, the implementation of corresponding low-cost and low-power receivers remains extremely challenging. In this project, we approach this challenge by joint consideration of algorithm and circuit implementation aspects.

Background:
For the past two decades, wireless communication standards have evolved at a rate that corresponds to doubling data rates every 18 months to continuously support more demanding applications for a rapidly growing number of users. In the future, the continuation of this trend requires significantly more complex signal processing and more communication bandwidth. Prominent examples of next generation wireless technologies are multiple-input multiple-output (MIMO) systems, ultra wideband (UWB) communications, and communication systems that employ relaying. Unfortunately, the excellent performance of such advanced communication systems is bought dearly at the expense of considerable complexity and power consumption. Until recently, the corresponding increase in circuit complexity has been absorbed by the higher levels of integration offered by advanced silicon process technologies. However, recently concerns have been raised that communication algorithms that approaching the fundamental performance limits of wireless systems suffer from a prohibitive complexity that exceeds the economic integration capabilities even of modern CMOS technologies. In addition to that, meeting the requirements on low power consumption and implementing highly complex signal processing algorithms in modern sub-100nm technologies becomes increasingly difficult and expensive as CMOS technology itself starts to reach its fundamental integration limits.

Research Goals:
The aim of this research program is to develop low-complexity and low-power integrated circuits and systems for next generation wireless communication standards. As opposed to the conventional approach, where algorithm development and circuit implementation are considered separately, our research focus is the joint consideration of both aspects. From an algorithm development perspective, we believe that this interdisciplinary approach is key to better understand the silicon implementation issues which is important to properly compare and optimize algorithms for hardware implementation. From a hardware perspective, we expect that properties of communication systems such as fault tolerance or specific signal statistics can be exploited to optimize yield, area, and power consumption of corresponding deep submicron integrated circuits.

Significance:
Wireless communication is widely recognized as a key factor that drives the global information society and often provides cost efficient solutions to boost infrastructure development in newly industrializing countries. However, the commercial success and the worldwide proliferation of next generation wireless technologies strongly depends on the availability of low-cost and low-power integrated transceiver solutions. We believe that this project can make key contributions to meeting the associated implementation challenges. Moreover, we believe that our research can yield new algorithms and corresponding low-power integrated circuits that can also be employed in applications other than wireless communications.
Direct link to Lay Summary Last update: 21.02.2013

Responsible applicant and co-applicants

Employees

Publications

Publication
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms
Dogan Ahmed Yasir, Braojos Ruben, Constantin Jeremy, Ansaloni Giovanni, Burg Andreas, Atienza David (2013), Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms, in Design, Automation and Test in Europe (DATE).
A 2.78 mm2 65 nm CMOS gigabit MIMO iterative detection and decoding receiver
Borlenghi F., Witte E.M., Ascheid G., Meyr H., Burg A. (2012), A 2.78 mm2 65 nm CMOS gigabit MIMO iterative detection and decoding receiver, in 38th European Solid-State Circuits Conference.
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS
Meinerzhagen P., Andersson O., Mohammadi B., Sherazi Y., Burg A., Rodrigues J.N. (2012), A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS, in IEEE European Solid-State Circuits Conference (ESSCIRC).
Layered detection and decoding in MIMO wireless systems
Preyss Nicholas, Burg Andreas, Studer C. (2012), Layered detection and decoding in MIMO wireless systems, in Conference on Design and Architectures for Signal and Image Processing (DASIP) 2012.
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon
Karakonstantis G., Roth C., Benkeser C., Burg A. (2012), On the exploitation of the inherent error resilience of wireless systems under unreliable silicon, in IEEE Design Automation Conference (DAC).
Replica bit-line technique for embedded multilevel gain-cell DRAM
Khalid M.U., Meinerzhagen P., Burg A. (2012), Replica bit-line technique for embedded multilevel gain-cell DRAM, in IEEE International NEWCAS Conference.
Review and classification of gain cell eDRAM implementations
Teman A., Meinerzhagen P., Burg A., Fish A. (2012), Review and classification of gain cell eDRAM implementations, in IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI).
Two-port low-power gain-cell storage array: Voltage scaling and retention time
Iqbal R., Meinerzhagen P., Burg A. (2012), Two-port low-power gain-cell storage array: Voltage scaling and retention time, in IEEE International Symposium on Circuits and Systems (ISCAS).
Synthesis Strategies for Sub-VT Systems
Meinerzhagen Pascal, Andersson Oskar, Sherazi Yasser, Burg Andreas, Rodrigues Joachim (2011), Synthesis Strategies for Sub-VT Systems, in Circuit Theory and Design (ECCTD), 2011 20th European Conference on, IEEE, USA.
Benchmarking of Standard-Cell Based Memories in the Sub-VT Domain in 65-nm CMOS Technology
Meinerzhagen Pascal, Sherazi Yasser, Burg Andreas, Rodrigues Joachim (2011), Benchmarking of Standard-Cell Based Memories in the Sub-VT Domain in 65-nm CMOS Technology, in Journal on Emerging and Selected Topics in Circuits and Systems, 1(2), 173-182.
Design and Failure Analysis of Logic-Compatible Multilevel Gain-Cell-Based DRAM for Fault-Tolerant VLSI Systems
Meinerzhagen Pascal, Andic Onur, Treichler Juerg, Burg Andreas (2011), Design and Failure Analysis of Logic-Compatible Multilevel Gain-Cell-Based DRAM for Fault-Tolerant VLSI Systems, in IEEE 21st Edition of the Great Lakes Symposium on VLSI (GLSVLSI), IEEE, USA.
A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder
Borlenghi F., Witte E.M., Ascheid G., Meyr H., Burg A. (2011), A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder, in IEEE Asian Solid-State Circuits Conference.
Benchmarking of Standard-Cell Based Memories in the Sub- V_{\rm T} Domain in 65-nm CMOS Technology
Meinerzhagen P., Sherazi S.M.Y., Burg A., Rodrigues J.N. (2011), Benchmarking of Standard-Cell Based Memories in the Sub- V_{\rm T} Domain in 65-nm CMOS Technology, in Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, 1(2), 173-182.
Synthesis strategies for sub-VT systems
Meinerzhagen P., Andersson O., Sherazi Y., Burg A., Rodrigues J. (2011), Synthesis strategies for sub-VT systems, in IEEE European Conference on Circuit Theory and Design (ECCTD).
A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
Roth C., Meinerzhagen P., Studer C., Burg A. (2010), A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS, in IEEE Asian Solid-State Circuits Conference (A-SSCC).
Area- and throughput-optimized VLSI architecture of sphere decoding
Wenk M., Bruderer L., Burg A., Studer C. (2010), Area- and throughput-optimized VLSI architecture of sphere decoding, in 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC).
Implementation of greedy algorithms for LTE sparse channel estimation
Maechler P., Greisen P., Sporrer B., Steiner S., Felber N., Burg A. (2010), Implementation of greedy algorithms for LTE sparse channel estimation, in Asilomar Conf. on Circuits, Systems, and Computers.
Low-complexity Seysen's algorithm based lattice reduction-aided MIMO detection for hardware implementations
Bruderer L., Senning C., Burg A. (2010), Low-complexity Seysen's algorithm based lattice reduction-aided MIMO detection for hardware implementations, in 44th Asilomar Conference on Signals, Systems and Computers.
Matching pursuit: Evaluation and implementatio for LTE channel estimation
Maechler P., Greisen P., Felber N., Burg A. (2010), Matching pursuit: Evaluation and implementatio for LTE channel estimation, in IEEE International Symposium on Circuits and Systems - ISCAS 2010.
MIMO transmission with residual transmit-RF impairments
Studer C., Wenk M., Burg A. (2010), MIMO transmission with residual transmit-RF impairments, in ITG Workshop on Smart Antennas (WSA).
The effect of unreliable LLR storage on the performance of MIMO-BICM
Novak C., Studer C., Burg A., Matz G. (2010), The effect of unreliable LLR storage on the performance of MIMO-BICM, in 44th Asilomar Conference on Signals, Systems and Computers.
Towards generic low-power area-efficient standard cell based memory architectures
Meinerzhagen P., Roth C., Burg A. (2010), Towards generic low-power area-efficient standard cell based memory architectures, in 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).
VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection
Bruderer L., Studer C., Wenk M., Seethaler D., Burg A. (2010), VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection, in International Symposium on Circuits and Systems (ISCAS 2010).
Multi-Core Architecture Design for Ultra Low Power Wearable Health Monitoring Systems
Dogan Ahmed, Constantin Jeremy, Ruggiero Martino, Burg Andreas, Atienza David, Multi-Core Architecture Design for Ultra Low Power Wearable Health Monitoring Systems, in IEEE/ACM 2012 Design Automation and Test in Europe conference (DATE), IEEE, USA.
On the Exploitation of the inherent error resilience of wireless systems under unreliable silicon
Karakonstantis Georgios, Roth Christoph, Benkeser Christian, Burg Andreas, On the Exploitation of the inherent error resilience of wireless systems under unreliable silicon, in IEEE Design Automation Conference (DAC), San Francisco, Design Automation Conference DAC, IEEE, USA.

Collaboration

Group / person Country
Types of collaboration
Embedded Systems Lab, EPFL Switzerland (Europe)
- in-depth/constructive exchanges on approaches, methods or results
- Publication
- Exchange of personnel

Associated projects

Number Title Start Funding scheme
153640 Design of Energy Efficient and Wireless Communication Systems under Unreliable Silicon 01.02.2015 Project funding (Div. I-III)

Abstract

Intorduction:Wireless communication is one of the key factors driving the global information and communication society. The development of the corresponding technology is reflected in an observation that is known as Edholm’s Law. This observation states that the evolution of wireless communication standards proceeds at a pace that corresponds to doubling data rates every 18 months. This incredible success has been enabled by advances in information theory and digital signal processing, combined with the ability to manufacture high-performance, low-power transceivers at low cost through very large scale (VLSI) integration.Currently, a number of new emerging applications, continue to create a demand for higher data rates, better quality of service, greater range, and higher system capacity to provide multimedia services to a rapidly growing number of users. To meet these demands, new communication paradigms are required to allow for a more bandwidth-efficient usage of the limited available radio-frequency spectrum. The use of multiple antennas on both sides of the wireless link has been widely recognized as the corresponding enabling technology since it allows for a linear increase in spectral efficiency with the minimum of the number of transmit and receive antennas. Unfortunately, these tremendous gains in spectral efficiency are bought dearly at the expense of considerable additional computational complexity, mostly in the receiver, but also in the transmitter. Until recently, this need for higher circuit complexity has been absorbed by advances in silicon process technology that have continued to enabled cost and power reduction by increasing the level of integration. Research challenge:Unfortunately, today, the complexity of straightforward implementations of high-rate MIMO wireless transceivers (with 4 or more antennas) or of even more complex multi-user MIMO systems exceeds the limits of economic, low-power integration even when using sub-100nm technologies. In addition to that, the complexity of the most interesting MIMO algorithms grows exponentially in the transmission rate, which leads to a double-exponential complexity increase over time (assuming Edholm’s Law holds). This rate is higher than the “only exponential” gains provided by the evolution of silicon process technology. In addition to the complexity challenges associated with MIMO technology, meeting the implementation challenges associated with modern sub-100nm technologies also becomes increasingly more difficult and expensive. As CMOS technology starts to reach its fundamental integration limits, new research challenges start to appear. For example, in a 45nm technology node, maintaining reasonably high yield has become increasingly difficult and the gains in terms of power consumption from using sub-100nm technologies have dropped significantly due to the dominant role of leakage currents. So far, these challenges have been addressed only on the circuit or technology level, without a view toward the algorithm or system level. A third research challenge in realizing circuits for next-generation wireless systems is the increasing need for flexibility to support a growing number of transmission schemes and wireless standards. The design of corresponding suitable hardware architectures is often summarized under the term software-defined radio.Project goals and approach:Mastering the challenges associated with the economic, low power implementation of next generation wireless communication systems in sub-100nm technologies requires a holistic, interdisciplinary approach which jointly considers system-level, algorithm, and VLSI implementation and technology aspects. In the proposed research program, we shall pursue such an innovative approach, focusing on the following three key research areas:1) Design of low-power, low-complexity algorithms and communication systems 2) Exploiting algorithm- and system-level aspects for power reduction and for achieving fault tolerance in wireless transceivers implemented in sub-100nm silicon process technologies3) Reconfigurable architectures for communication systemsIn the first research area, we will consider algorithm and system-level aspects of MIMO wireless systems with a view towards their efficient low-power VLSI implementation. To this end, we shall study low-complexity receiver algorithms with close-to optimum performance and we shall conduct research on how to model and optimize the energy efficiency of wireless transceivers on the overall system level by includes effects ranging from leakage in sub-100nm circuits to the power required for retransmissions triggered by the medium-access-control layer.In the second research area, we shall start from the process technology and from the circuit-level perspective to address the problems of reducing power consumption and improving the yield and noise tolerance in sub-100nm wireless transceivers. To this end, we shall show how one can incorporate knowledge about the wireless system into the circuit design and optimization process to reduce power and to achieve fault-tolerant designs that achieve higher yield.In the third part of this research program, we shall address the problem of providing reconfigurable hardware architectures that can be used for software-defined-radio and for prototyping applications for wireless systems. To this end, we shall consider the use of multi-processor systems-on-chip employing network-on-chip based interconnect architectures. In our research, will devise such an architecture that is ssuitable for prototyping high-rate MIMO transceivers. Significance of the researchIn summary, we expect that the result of our research will contribute to the evolution of wireless communication systems by enabling efficient, low-power implementations of the required complex algorithms in sub-100nm technologies.
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