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Compiler Technology for Customisable Embedded Processors

English title Compiler Technology for Customisable Embedded Processors
Applicant Pozzi Laura
Number 113812
Funding scheme Project funding (Div. I-III)
Research institution Istituto di sistemi informatici (SYS) Facoltà di scienze informatiche
Institution of higher education Università della Svizzera italiana - USI
Main discipline Information Technology
Start/End 01.10.2006 - 30.09.2008
Approved amount 95'080.00
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Keywords (9)

Compilers; Embedded Systems; Instruction Set Design; Graph Matching; Instruction Set Extensions; Customisation; Customisable; Code transformation; Hw Sw Codesign

Lay Summary (English)

Lay summary
Processor Customisation is an important technique aimed at meeting the stringent requirements of Embedded Processor design: a blend of high performance, low power, and fast time to market that is seldom found outside the embedded applications world. Customisable Processors are quickly becoming available---examples are Tensilica Xtensa and ARC ARCtangent---offering the possibility to extend a base Instruction Set with Instruction Set Extensions (ISEs), so that critical parts of the application can be run in hardware, in Application-specific Functional Units (AFUs).

The automation offered by these processor toolchains is increasing, and, in particular, techniques have been proposed to identify the most profitable ISEs for a given application, from source code analysis.
This automation trend has a number of consequences, and in particular it modifies profoundly the role of a traditional compiler. In fact, while the compiler was ``simply'' used to translate high-level code into machine code, now it is given the capability of choosing the underling machine and then compile onto it. This raises questions, such as ``are traditional compiler techniques apt to this new role''?

Automated ISE techniques have been designed so far---by the applicants, among others, rather actively--- as independent techniques, not interwoven with compiler design. On the other hand, further research by the main applicant unveiled that traditional compiler techniques are not fit for this new compiler role: compilers in this new scenario must take new decisions. As an example, the compiler must now expose ISE identification, it must be equipped with advanced instruction selection techniques for reuse of ISEs, and a study of the best positioning of ISE within the compiler flow is also necessary. In short, when dealing with Customisable Processors, ISE identification techniques and compilers cannot be designed independently.

This work will design a customisable processor complier, investigate on its new role and design new algorithms and techniques for: ISE identification, ISE reuse among different applications, exposition of ISEs. It will also build a full compilation and simulation framework for precisely assessing results.
Direct link to Lay Summary Last update: 21.02.2013

Responsible applicant and co-applicants


Name Institute

Associated projects

Number Title Start Funding scheme
156397 Magic ISEs: Enlarging the Scope of Automatic Instruction Set Extension 01.11.2014 Project funding (Div. I-III)
188613 ADApprox: Towards Application-Driven Approximate Logic Synthesis 01.10.2020 Project funding (Div. I-III)