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Gbps Decoders for Polar Codes in 5G Networks

English title Gbps Decoders for Polar Codes in 5G Networks
Applicant Burg Andreas Peter
Number 169443
Funding scheme Project funding (Div. I-III)
Research institution Laboratoire de circuits pour télécommunications EPFL - STI - IEL - TCL
Institution of higher education EPF Lausanne - EPFL
Main discipline Information Technology
Start/End 01.10.2016 - 30.09.2017
Approved amount 98'424.00
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All Disciplines (2)

Discipline
Information Technology
Electrical Engineering

Keywords (4)

Channel Coding; VLSI design; Integrated Circuits; Polar Codes

Lay Summary (German)

Lead
POLAR CODES sind eine neue Art der Codierug für die Korrektur von Uebertragungsfehlern in der drahtlosen Kommunikation und bei Speichermedien (z.B. Festplatten oder Flash Disks). Im Genesatz zu etablierten Codes (z.B. Turbo oder LDPC codes) die in heutigen Standards eingesetzt werden bieten Polar Codes viele Vorteile (z.B. bessere Fehlerkorrektur oder die Fähigkeit die Datenrate sehr feingranular an die Kapazität des Kanals anzupassen). Daher ist man bestrebt für die Entwicklung der nächsten Mobilfunkgeneration (5G) Polar Codes zu verwenden. Eine wesentliche Herausforderung besteht dabei darin auch effiziente und stromsparende Dekoder bauen zu können.
Lay summary

Seit einiger Zeit ist klar, dass Polar Codes ein wichtiger Bestandteil der nächsten Mobilfunkgeneration sein werden. Entsprechende erste Artikel wurden dazu kürzlich verabschiedet und es wird erwartet dass Polar Codes sich noch an weiteren wesentlichen Stellen des Standards etablieren werden. Trotz dieses Erfolges liegt eine grosse Herausforderung immernoch in der Realisierung stromsparender, effizienter, und leistungsfähier Dekoder. Unser Ziel in diesem Projekt besteht darin,entsprechende Algorithmen und die zugehörigen Hardware Architekturen zu entwickeln. Hiermit treiben wir nicht nur den Erfold von Polar Codes in der Standartisierung der 5. Mobilfunkgeneration voran, sondern tragen auch ganz konkret zur Verfügbarkeit stromsparender Mobilfunkgeräte bei. 

Im speziellen konzentriert sich unsere Arbeit in diesem Projekt auf einen Algorithmus der als "Successive Cancellation List Decoding" bekannt ist. Dieser Algorithmus garantiert eine ausgezeichnete Fehlerkorrektur, bereitet aber Probleme wenn es darum geht hohe Datenraten oder kurze Latenzen in der Dekodierung zu erreichen. In unserer Arbeit entwickeln wir Lösungsvorschläge für dieses Problem. Dabei bauen wir auf den Resultaten eines vorangegangenen projektes auf. 

 

Direct link to Lay Summary Last update: 13.01.2017

Responsible applicant and co-applicants

Employees

Publications

Publication
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes
Giard Pascal, Balatsoukas-Stimming Alexios, Muller Thomas Christoph, Bonetti Andrea, Thibeault Claude, Gross Warren J., Flatresse Philippe, Burg Andreas (2017), PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes, in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 7(4), 616-629.
Blind detection of polar codes
Giard Pascal, Balatsoukas-Stimming Alexios, Burg Andreas (2017), Blind detection of polar codes, in 2017 IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France.
A Comparison of Polar Decoders with Existing LDPC and Turbo Decoders
Balatsoukas-Stimming Alexios, Giard Pascal, Burg Andreas (2017), A Comparison of Polar Decoders with Existing LDPC and Turbo Decoders, in IEEE Wireless Commun. and Netw. Conf. (WCNC).
A multi-Gbps unrolled hardware list decoder for a systematic polar code
Giard Pascal, Balatsoukas-Stimming Alexios, Muller Thomas Christoph, Burg Andreas, Thibeault Claude, Gross Warren J. (2016), A multi-Gbps unrolled hardware list decoder for a systematic polar code, in 2016 50th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USAIEEE, IEEEXplore.
Hardware implementation aspects of polar decoders and ultra high- speed LDPC decoders
Balatsoukas Stimming Alexios (2016), Hardware implementation aspects of polar decoders and ultra high- speed LDPC decoders, EPFL, EPFL.
Modulation, Coding, and Receiver Design for Gigabit mmWave Communication
Preyss Nicholas (2016), Modulation, Coding, and Receiver Design for Gigabit mmWave Communication.

Collaboration

Group / person Country
Types of collaboration
Ecole de technologie supérieure LaCIME Canada (North America)
- in-depth/constructive exchanges on approaches, methods or results
- Publication
McGill University ISIP Canada (North America)
- in-depth/constructive exchanges on approaches, methods or results
- Publication
ST Microelectronics France (Europe)
- Research Infrastructure
- Industry/business/other use-inspired collaboration
Huawei Canada (North America)
- in-depth/constructive exchanges on approaches, methods or results
- Industry/business/other use-inspired collaboration
EPFL IC ISC LTHC/LTHI Switzerland (Europe)
- in-depth/constructive exchanges on approaches, methods or results

Scientific events

Active participation

Title Type of contribution Title of article or contribution Date Place Persons involved
Information Theory and Applications Workshop (ITA) Individual talk Polar codes and APSK modulation-Just good friends 12.02.2017 San Diego, CA, United States of America Balatsoukas Stimming Alexios Konstantinos; Giard Pascal; Burg Andreas Peter;


Communication with the public

Communication Title Media Place Year
Media relations: radio, television Comments on 5G RTS 1ère Western Switzerland 2017
Media relations: print media, online media Meet the chips behind 5G’s polar codes Horizons: The Swiss Research Magazine Rhaeto-Romanic Switzerland Western Switzerland German-speaking Switzerland Italian-speaking Switzerland 2017

Associated projects

Number Title Start Funding scheme
175813 Energy Proportional Decoding of Polar Codes for 5G with Variable Complexity Algorithms 01.02.2018 Project funding (Div. I-III)
149447 Efficient Application Specific Integrated Circuits for Decoding Polar Codes 01.05.2014 Project funding (Div. I-III)

Abstract

Polar codes are a new type of codes for forward error correction that can achieve the capacity of symmetric binary-input discrete memoryless point-to-point channels and of other, practically relevant channels such as the additive white Gaussian noise channel. Moreover, polar codes have also been shown to be capacity achieving for multi-terminal communication scenarios, such as relay channels and broadcast channels, as well as lossy and lossless source coding. Contrary to other, well established, capacity achieving codes, polar codes have a systematic construction that yields well understood performance guarantees. Furthermore, the encoding and a low-complexity, capacity achieving decoding procedure of polar codes can be realized with an, at first sight, favorable complexity that scales only according to N*log(N), where N is the length of the code block.Despite the favorable complexity scaling, achieving very high-throughput and low-latency decoding with successive cancellation (SC) based decoding algorithms is challenging in practice due to the sequential nature of the SC algorithm, which limits the achievable degree of parallel processing. Due to the nested structure of polar codes, however, it is possible to decode multiple codeword bits simultaneously, which form sub-codes within the polar code, with various low-complexity code-specific and close-to-optimal constituent decoders. This approach can reduce the decoding latency significantly, leading to decoders with throughputs of over 1 Gbit/s, while having little to no effect on the error correcting performance of the code. An alternative approach is to use belief propagation (BP) decoding, which can be parallelized massively, instead of SC decoding. BP decoders for polar codes have been proposed that can achieve throughputs of multiple Gbit/s, at the cost of significantly increased hardware complexity with respect to SC decoders and, so far, an SNR performance penalty.Unfortunately, even though SC and BP polar decoders have been shown to enable the design of low-latency and high-throughput hardware decoders, they have a considerable disadvantage compared to other competing codes: they degrade the error correction capability of polar codes, especially for short block lengths. As a direct consequence, polar codes with standard SC or BP decoding are not immediately competitive with other competing codes of similar block lengths. Fortunately, polar codes with more powerful decoding algorithms, such as the SC list (SCL) algorithm, have been shown to outperform competing coding schemes, such as LDPC codes, in a variety of scenarios. While there has been some work devoted to the design of efficient SCL hardware decoders, including our own previous research efforts, these decoders have not yet achieved the low-latency and high-throughput operation of their SC and BP counterparts, mainly because the constituent decoder ideas that enable fast SC decoding are unfortunately not directly applicable to SCL decoding without error correcting performance loss.With this project, we are proposing a 1 year research effort as a continuation of our previous 2 year project, which mainly focuses on two pressing research issues that we have identified during our previous work on the topic. First, we aim to perform a systematic comparison of the error correcting performance of polar codes under various decoding algorithms (SC, BP, and SCL) with LDPC and Turbo codes used in existing communications standards. This comparison will enable us to identify the decoding algorithm and parameters (e.g., list size for SCL decoding) that need to be used in each scenario in order to match (or exceed) the error correcting performance of existing state-of-the-art codes. The second goal is to derive efficient, high-throughput, and flexible (i.e., multiple supported block lengths and code rates) SCL hardware decoders through both architectural and algorithmic optimizations.
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