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Efficient Application Specific Integrated Circuits for Decoding Polar Codes

Gesuchsteller/in Burg Andreas Peter
Nummer 149447
Förderungsinstrument Projektförderung (Abt. I-III)
Forschungseinrichtung Laboratoire de circuits pour télécommunications EPFL - STI - IEL - TCL
Hochschule EPF Lausanne - EPFL
Hauptdisziplin Informatik
Beginn/Ende 01.05.2014 - 31.07.2016
Bewilligter Betrag 135'450.00
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Alle Disziplinen (2)

Disziplin
Informatik
Elektroingenieurwesen

Keywords (4)

Integrated Circuits; Channel Coding; VLSI design; Polar Codes

Lay Summary (Deutsch)

Lead
Forward Error Correction (FEC) Codes sind ein wesentliche Bestandteil aller modernen Kommunikations- und Speichersysteme. Im wesentlichen dienen diese Codes dazu, eine (nahezu) fehlerfreie Datenuebertragung bzw. Datensicherung trotz Stoerungen zu erreichen. Hierzu wird den eigentlichen Daten (information-bits) Redundanz zur Fehlerkorrektur hinzugefuegt. In den vergangenen Jahrzehnten wurden unterschiedliche Codes entwickelt die sich stark durch Ihre Effizienz, Anwendungsgebiete, und Komplexitaet unterscheiden. Die sogenannten Polar codes stellen die neueste Errungenschaft im Bereich der Kodierungstheorie dar. Sie zeichnen sich besonders durch ihre Struktur aus, die eine elegante analytische Behandlung ermoeglicht und durch neue Strategien zur Dekodierung.
Lay summary
Fuer den praktischen Einsatz von Polar Codes muss neben der theoretischen Performance auch die Realisierbarkeit entsprechender hardware- und energie-effizienter
Decoder gewaehrleistet sein. Waehrend fuer andere Codes (e.g., Turbo codes und LDPC codes) bereits Jahre der Forschung in entsprechende Hardwarestrukturen
investiert wurden, ist dieses Gebiet fuer Polar codes noch fast vollstaendig unerforschat. Ziel dieses Projektes ist es, daher entsprechende Algorithmen und
die dazu gehoerigen Schaltungen zu entwickeln und somit den Weg fuer den praktischen Einsatz dieser neuen Art von Codes in realen Systemen zu ebnen.
Direktlink auf Lay Summary Letzte Aktualisierung: 02.04.2014

Verantw. Gesuchsteller/in und weitere Gesuchstellende

Mitarbeitende

Publikationen

Publikation
Hardware decoders for polar codes: An overview
Giard P., Sarkis G., Balatsoukas-Stimming A., Fan Y., Tsui C.-Y., Burg A., Thibeault C. (2016), Hardware decoders for polar codes: An overview, in Proc. of the Int. Conference on Circuits and Systems (ISCAS), Montreal, CanadaIEEE, US.
Low-complexity polar decoders for low-rate codes
Giard P., Balatsoukas-Stimming A., Sarkis G., Thibeault C., Gross W. J. (2016), Low-complexity polar decoders for low-rate codes, in Springer Journal of Signal Processing Systems, 1.
An FPGA-based accelerator for rapid simulation of SC decoding of polar codes
Wüthrich J., Balatsoukas-Stimming A., Burg A. (2015), An FPGA-based accelerator for rapid simulation of SC decoding of polar codes, in Proc. of the Int. Conference on Electronics, Circuits, and Systems, IEEE, US.
LLR-Based Successive Cancellation List Decoding of Polar Codes
Balatsoukas-Stimming Alexios, Parizi Mani Bastani, Burg Andreas (2015), LLR-Based Successive Cancellation List Decoding of Polar Codes, in IEEE TRANSACTIONS ON SIGNAL PROCESSING, 63(19), 5165-5179.
On Metric Sorting for Successive Cancellation List Decoding of Polar Codes
Balatsoukas-Stimming Alexios, Parizi Mani Bastani, Burg Andreas (2015), On Metric Sorting for Successive Cancellation List Decoding of Polar Codes, in Proc. of the Int. Symposium on Circuits and Systems (ISCAS), Lisbon, PortugalIEEE, US.
The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes
Mu J., Vosoughi A., Andrade J., Balatsoukas-Stimming A., Karakonstantis G., Burg A., Falcao G., Silva V., Cavallaro J. R. (2015), The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes, in Proc. of the Asilomar Conf. on Circuits, Systems, and Computers, Pacific Grove, USAIEEE, US.
A Low-Complexity Improved Successive Cancellation Decoder for Polar Codes
Afisiadis Orion, Balatsoukas-Stimming Alexios, Burg Andreas (2014), A Low-Complexity Improved Successive Cancellation Decoder for Polar Codes, in Asilomar Conf. on Circuits, Systems, and Computers, Pacific Grove, USAIEEE, US.
Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage
Balatsoukas-Stimming Alexios, Burg Andreas (2014), Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage, in IEEE COMMUNICATIONS LETTERS, 18(5), 849-852.
Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes
Balatsoukas-Stimming Alexios, Karakonstantis Georgios, Burg Andreas (2014), Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes, in Proc. of the Int. Symposium on Information Theory (ISIT), Honolulu, USAIEEE, US.
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel
Balatsoukas-Stimming Alexios, Burg Andreas (2014), Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel, in Int. Symposium on Information Theory and Applications (ISITA), Melbourne, AustraliaIEEE, US.
Hardware Architecture for List Successive Cancellation Decoding of Polar Codes
Balatsoukas-Stimming Alexios, Raymond Alexandre J., Gross Warren J., Burg Andreas (2014), Hardware Architecture for List Successive Cancellation Decoding of Polar Codes, in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 61(8), 609-613.
LLR-BASED SUCCESSIVE CANCELLATION LIST DECODING OF POLAR CODES
Balatsoukas-Stimming Alexios, Parizi Mani Bastani, Burg Andreas (2014), LLR-BASED SUCCESSIVE CANCELLATION LIST DECODING OF POLAR CODES, in Proc. of the Int. Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ItalyIEEE, US.
A multi-Gbps unrolled hardware list decoder
Giard P., Balatsoukas-Stimming A., Burg A., Thibeault C., Gross W. J., A multi-Gbps unrolled hardware list decoder, in Proceedings of the Asilomar Conference on Signals, Systems, and Computers, Pacific GroveIEEE, US.

Zusammenarbeit

Gruppe / Person Land
Formen der Zusammenarbeit
EPFL IC ISC LTHC/LTHI Schweiz (Europa)
- vertiefter/weiterführender Austausch von Ansätzen, Methoden oder Resultaten
- Publikation

Wissenschaftliche Veranstaltungen

Aktiver Beitrag

Titel Art des Beitrags Titel des Artikels oder Beitrages Datum Ort Beteiligte Personen
ISIS Workshop on Energy-efficiency in Error-Correction Coding Vortrag im Rahmen einer Tagung Complexity and Energy Efficiency of LDPC Decoders and an Initial Comparison to Polar Codes 08.06.2016 Télécom ParisTech , Frankreich Burg Andreas Peter; Balatsoukas Stimming Alexios Konstantinos;
Huawei International Workshop on Polar Codes at ISIT 2015 Vortrag im Rahmen einer Tagung Hardware Decoders for Polar Codes 13.06.2015 Hongkong, Hongkong Burg Andreas Peter;


Selber organisiert

Titel Datum Ort
Special Session on "Polar-Code Decoders" at ISCAS 2016 23.05.2016 Montreal, Kanada

Auszeichnungen

Titel Jahr
2nd Place in Student Paper Contest of ICECS 2015 with a paper based on a Masters Thesis conducted in under the umbrella of this project. Paper Title: “An FPGA-based accelerator for rapid simulation of SC decoding of polar codes" 2015

Verbundene Projekte

Nummer Titel Start Förderungsinstrument
169443 Gbps Decoders for Polar Codes in 5G Networks 01.10.2016 Projektförderung (Abt. I-III)
175813 Energy Proportional Decoding of Polar Codes for 5G with Variable Complexity Algorithms 01.02.2018 Projektförderung (Abt. I-III)

Abstract

Polar codes are a new type of codes for forward error correction that can achieve the capacity of many practically relevant channels. Polar codes differentiate themselves from other, well established capacity achieving codes by the fact that they follow a systematic construction that yields well understood performance guarantees. Furthermore, the encoding and a capacity achieving decoding procedure of polar codes can be realized with an, at first sight, favorable complexity. Hence, these codes have received significant attention in the information-theory community. With this project, we are proposing a 2 year research effort that focuses on the practically relevant implementation aspects of polar codes with the objective to realize corresponding decoders that are competitive to decoders for established codes, both in terms of performance and complexity. To this end, we consider jointly both the algorithm and the VLSI architecture side. We believe that besides the actual decoder implementations itself these investigations will be instrumental in answering the question if and how polar codes can play a major role in future wireless and wireline communication standards. Our results will be particularly important when considering this new type of codes as competitors for established, already very well performing codes such as LDPC and Turbo codes in applications for which either low power or very high throughput are key requirements.
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