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Magic ISEs: Enlarging the Scope of Automatic Instruction Set Extension

Gesuchsteller/in Pozzi Laura
Nummer 156397
Förderungsinstrument Projektförderung (Abt. I-III)
Forschungseinrichtung Facoltà di scienze informatiche Università della Svizzera italiana
Hochschule Università della Svizzera italiana – USI
Hauptdisziplin Informatik
Beginn/Ende 01.11.2014 - 31.08.2018
Bewilligter Betrag 450'995.00
Alle Daten anzeigen

Keywords (6)

Reconfigurable Processors; Automatic Instruction Set Extensions; Customizable Processors; ASIPs; Accelerators; Heterogeneous Computing

Lay Summary (Italienisch)

I processori customizzabili sono processori che possono essere ottimizzati a seconda della applicazione che devono eseguire. Customizzando un processore si puo' ottenere una performance molto migliore, e un consumo di potenza molto piu' basso, rispetto a quello che si otterrebbe usando un processore general-purpose—e quindi non customizzato.Nello specifico, un modo efficiente di customizzare un processore e' quello di affiancargli dell’hardware aggiuntivo, nel quale si possa eseguire una parte importante della applicazione, in maniera dedicata. L’identificazione di queste parti critiche dell’applicazione, cosi' come la loro implementazione in hardware, richiedono pero' tipicamente l’intervento manuale del progettista.In questo progetto, si identificano algoritmi che siano in grado di selezionare e sintetizzare le parte critiche di una applicazione in modo automatico.
Lay summary
Il progetto quindi si propone di avanzare lo stato dell'arte nell'identificazione e nella sintesi automatica di acceleratori.
Direktlink auf Lay Summary Letzte Aktualisierung: 21.10.2014

Verantw. Gesuchsteller/in und weitere Gesuchstellende


Verbundene Projekte

Nummer Titel Start Förderungsinstrument
122158 Architectural design and exploration of innovative coarse grained reconfigurable arrays 01.10.2008 Projektförderung (Abt. I-III)
113812 Compiler Technology for Customisable Embedded Processors 01.10.2006 Projektförderung (Abt. I-III)


This project aims at enlarging the scope of automatic Instruction SetExtension (ISE). ISEs are special, complex instructions that are addedto a processor in order to make it better targeted to a particularapplication to be served, resulting in higher performance and betterpower efficiency. Automatic ISE is the process of devisingsuch extensions automatically from the application source code. Thestate of the art of automatic ISE indentification has advancedconsiderably in the past 15 years, including several papers by theapplicant. On the other hand, several challenges still lay ahead, andthe challenges here identified were inspired by reading a recentpaper, that set out to understand the sources ofinefficiencies of general-purpose processors, both in terms ofperformance and power. An important consideration is made at the endof the paper study: the only way to bridge the gap between swexecution, and dedicated hardware execution, is to specializethe baseline processor. The paper indeed adds more and more complexinstruction to a baseline processor under consideration, identifyingthese instructions manually and terming them 'magic' because oftheir complexity, and achieving some outstanding performanceimprovements. This proposal aims at identifying those sameinstructions, but in an automatic way; i.e., devisingalgorithms that can identify and synthesize those instructions withoutprogrammer intervention. The charachteristics that make theseinstructions special, and beyond the current challenges of state ofthe art tools, are: they cluster 100s of original operations into asingle instruction, they are tightly connected to custom data storageelements, they are built on top of vectorized code. These are indeedthe challenges that this proposal wants to tackle. This proposal aimstherefore at extending the state of the art in Instruction SetExtensions methodologies, combining them with compiler transformationssuch as vectorization, and finally analyzing the tradeoff of mappingsuch extensions on reconfigurable logic.